RFIC Layout Designer (Starshield Silicon)

<div class="content-intro"><p>SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of&nbsp;enabling human life on Mars.</p></div><p><strong><span data-contrast="auto">RFIC&nbsp;LAYOUT DESIGNER&nbsp;(STARSHIELD SILICON)</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">Starshield leverages SpaceX’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As a RFIC&nbsp;Layout&nbsp;Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security.&nbsp;</span><span data-ccp-props="{}">&nbsp;</span></p> <p><span data-contrast="auto">We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world-class cross-disciplinary teams (systems architecture, ASIC design, firmware, pre-silicon verification, post-silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical&nbsp;level and&nbsp;will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs. </span><span data-ccp-props="{}">&nbsp;</span></p> <p><strong><span data-contrast="auto">RESPONSIBILITIES:</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li><span data-contrast="auto">Work with the integrated circuit designers and chip leads to&nbsp;determine&nbsp;the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging&nbsp;engineers&nbsp;to determine pad locations</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Work with EDA suppliers to trial new tools and features</span><span data-ccp-props="{}">&nbsp;</span></li> <li><span data-contrast="auto">Generate guides and demos for others in the team to showcase improvements in layout technique</span><span data-ccp-props="{}">&nbsp;</span></li> </ul> <p><strong><span data-contrast="auto">BASIC QUALIFICATIONS:</span></strong><span data-ccp-props="{}">&nbsp;</span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Bachelor’s degree in electrical or computer engineering or</span><span data-