New Graduate Engineer, Silicon Engineering

<div class="content-intro"><p>SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of&nbsp;enabling human life on Mars.</p></div><p><span data-ogsc="rgb(0, 0, 0)"><strong>NEW GRADUATE ENGINEER, SILICON ENGINEERING</strong></span></p> <p><span data-ogsc="rgb(0, 0, 0)">Are you an engineering student graduating in fall or this upcoming spring/summer that is looking for full-time employment after graduation? We are looking for engineers to help us develop next generation silicon for SpaceX. The team is hiring engineers from pre-silicon through post-silicon across many disciplines in RF/Analog IC, RTL design, design verification, physical design, DFT, validation and more using state-of-the-art tools and methodologies. The ideal candidate will be a hands-on self-starter who can execute the steps required to fully design and verify complex designs.</span></p> <p><span data-ogsc="rgb(0, 0, 0)">Full-time employment is available working on our Starlink program in Palo Alto (CA), Irvine (CA), or Redmond (WA).&nbsp;</span></p> <p><span data-ogsc="rgb(0, 0, 0)"><strong>RESPONSIBILITIES:</strong></span></p> <ul> <li data-ogsc="rgb(0, 0, 0)">ASIC/FPGA Design &amp; Verification</li> <ul> <li data-ogsc="rgb(0, 0, 0)">Participate in all phases of ASIC/FPGA design and verification flows</li> <li data-ogsc="rgb(0, 0, 0)">Contribute towards design architecture, RTL implementation and/or verification, and emulation</li> <li data-ogsc="rgb(0, 0, 0)">Bring-up and validate ASICs and FPGAs in the lab (write embedded software using C/C++ and/or Python)</li> <li data-ogsc="rgb(0, 0, 0)">Hands-on self-starter who can execute the steps required to fully verify a complex digital design</li> </ul> <li data-ogsc="rgb(0, 0, 0)">RF/Analog IC Design</li> <ul> <li data-ogsc="rgb(0, 0, 0)">Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains</li> <li data-ogsc="rgb(0, 0, 0)">Derive specifications for the RFIC subsystems and circuits</li> <li data-ogsc="rgb(0, 0, 0)">Develop RF/microwave circuits in state-of-the-art SiGe or CMOS processes</li> <li data-ogsc="rgb(0, 0, 0)">Perform IC floor planning and layout</li> </ul> <li data-ogsc="rgb(0, 0, 0)">Digital Signal Processing</li> <ul> <li data-ogsc="rgb(0, 0, 0)">Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)</li> <li data-ogsc="rgb(0, 0, 0)">Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers</li> </ul> <li data-ogsc="rgb(0, 0, 0)">Physical Design</li> <ul> <li data-ogsc="rgb(0, 0, 0)"> <div>Perform synthesis and physical implementation steps (synthesis, floor planning, place and route, timing/noise analysis, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)</div> </li> <li data-ogsc="rgb(0, 0, 0)">Develop/improve physical design methodologies and automation scripts for various implementation steps</li> <li data-ogsc="rgb(0, 0, 0)">Participate in silicon tapeouts in advanced technology nodes for future Starlink SOCs</li> </ul> </ul> <p><span data-ogsc="rgb(0, 0, 0)"><strong>BASIC QUALIFICATIONS:</strong></span></p> <ul> <li>Graduating with a bachelor’s degree, master’s degree or PhD in 2026 or 2027</li> <li>Bachelor’s degree in an engineering discipline, mathematics or physics</li> <li>Experience working with ASIC, SOC, FPGA, RFIC, or MMIC</li> </ul> <p><span data-ogsc="rgb(0, 0, 0)"><strong>PREFERRED SKILLS AND EXPERIENCE:</strong></span></p> <ul> <li data-ogsc="rgb(0, 0, 0)">Understanding of computer architecture</li> <li data-ogsc="rgb(0, 0, 0)">Experience in one or more of the following areas:</li>